The present invention generally relates to the field of semiconductor tests, and more specifically relates to an Automatic Test Pattern Generation (ATPG) scan-based structural test.
Due to (among other reasons) increased operating frequencies and increased back end metal layers, delay related defects in random logic are becoming a more significant contributor to the overall defect density in semiconductor manufacturing. This trend in delay defect density is causing additional need to test for and reject die whose speed performance is inadequate due to the presence of such defects. Screening for delay defects has traditionally been performed via at-speed functional testing of the device. However, due to an increased ratio of internal nodes to external control and observation points (primary inputs and outputs, respectively), it is becoming increasingly difficult to create functional test patterns in a time and cost efficient manner.
In order to increase the testability of device, scan chains are often used. A scan chain is a connection of sequential elements converted into a shift register, which simplifies structural testing by providing additional control and observe points to internal nodes within a design. Generally, scan chain operations consist of shifting in test data, capturing system data and shifting out system responses.
In a functional test, functional vectors are used to simulate the design's functionality. Functional vectors are less efficient, grow exponentially in size as the design grows, deliver lower coverage, and are far more difficult to diagnose than functional tests.
Scan based structural testing is an effective solution for testing for delay defects as an alternative to functional testing. The most commonly practiced method of generating test vectors to screen delay faults relies on the transition delay fault (TDF) model. In a TDF fault model, a node can be either slow-to-rise (STR) or slow-to-fall (STF). In a conventional ATPG process, for each node in the circuit, a test vector is created to detect both a slow-to-rise and a slow-to-fall transition fault. This has proven to be an effective technique toward high quality test patterns. However, too many test vectors are generated and the processing time required to generate the vectors is too high for this test method to be cost effective.
Most current approaches toward reducing the test vector count are focused on compression techniques that try to either: 1) remove any redundancies in the patterns; or 2) group multiple patterns that do not have overlapping constraints. These compression techniques typically reduce the pattern count, which is desirable. However, the reduction comes at the price of increased pattern generation times. To combat the increased run times, techniques which have been used in the industry include: distributing the ATPG process to multiple computers; and using more efficient algorithms that take fewer steps to converge on a needed test vector.
While these approaches are not necessarily unacceptable, there is an efficiency barrier that will not be overcome by these techniques. True efficiency cannot be achieved due to the fact that a conventional transition delay fault model assumes that a manufacturing defect will cause either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault. In reality, the vast majority of timing-related defects will cause both a slow-to-rise and a slow-to-fall transition timing fault. Because of the discrepancy between the real manufacturing defect and the idealized faulty circuit behavior, conventional transition delay fault models generate unnecessary test vectors, and cause unnecessary processing time to be spent targeting faults that will never be detected in the manufacturing test.